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1/20 october 2002 M41T80 serial access rtc with alarms features summary 2.0 to 5.5v clock operating voltage counters for tenths/hundredths of seconds, seconds, minutes, hours, day, date, month, year, and century serial interface supports i 2 c bus (400khz) programmable alarm and interrupt function low operating current of 200a operating temperature of C40 to 85c figure 1. logic diagram figure 2. 8-pin soic package table 1. signal names scl v cc M41T80 v ss sda f 32k irq/out/sqw xi xo ai07005 xi oscillator input xo oscillator output irq /out/ sqw interrupt / output driver / square wave (open drain) sda serial data input/output scl serial clock input f 32k 32khz square wave output (open drain) v cc supply voltage v ss ground 8 1 so8 (m)
M41T80 2/20 table of contents summary description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 8-pin soic connections (figure 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 block diagram (figure 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 absolute maximum ratings (table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 dc and ac parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 operating and ac measurement conditions (table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ac measurement i/o waveform (figure 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 capacitance (table 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 dc characteristics (table 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 crystal electrical characteristics (table 6.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 serial bus data transfer sequence (figure 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 acknowledgement sequence (figure 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 bus timing requirements sequence (figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 ac characteristics (table 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 read mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 slave address location (figure 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 read mode sequence (figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 alternative read mode sequence (figure 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 write mode sequence (figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 timekeeper? registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 timekeeper? register map (table 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 full-time 32khz square wave output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 century bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 alarm interrupt reset waveform (figure 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 alarm repeat modes (table 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 square wave output frequency (table 10.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 century bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 preferred power-on default. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 preferred power-on default values (table 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3/20 M41T80 summary description the M41T80 serial access timekeeper ? sram is a low power serial rtc with a built-in 32.768 khz oscillator (external crystal controlled). eight registers (see table 8, page 13) are used for the clock/calendar function and are configured in binary coded decimal (bcd) format. an additional 12 registers provide status/control of alarm, 32khz output, and square wave functions. addresses and data are transferred serially via a two line, bi- directional i 2 c interface. the built-in address reg- ister is incremented automatically after each write or read data byte. functions available to the user include a time-of- day clock/calendar, alarm interrupts, 32khz out- put, and programmable square wave output. the eight clock address locations contain the century, year, month, date, day, hour, minute, second and tenths/hundredths of a second in 24 hour bcd for- mat. corrections for 28, 29 (leap year - valid until year 2100), 30 and 31 day months are made auto- matically. the M41T80 is supplied in an 8-pin soic. figure 3. 8-pin soic connections note: 1. open drain output. figure 4. block diagram note: 1. open drain output 2 3 45 6 8 7 1 irq/out/sqw (1) sda scl v ss xo f 32k (1) xi v cc M41T80 ai07006 real time clock calendar rtc w/alarm square wave irq/out/sqw (1) f 32k (1) af sda scl i 2 c interface 32khz oscillator crystal ai07007
M41T80 4/20 maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect de- vice reliability. refer also to the stmicroelectronics sure program and other rel- evant quality documents. table 2. absolute maximum ratings note: 1. reflow at peak temperature of 215c to 225c for < 60 seconds (total thermal budget not to exceed 180c for between 90 t o 120 seconds). sym parameter value unit t stg storage temperature (v cc off, oscillator off) C55 to 125 c v cc supply voltage C0.3 to 7 v t sld (1) lead solder temperature for 10 seconds 260 c v io input or output voltages C0.3 to vcc+0.3 v i o output current 20 ma p d power dissipation 1 w
5/20 M41T80 dc and ac parameters this section summarizes the operating and mea- surement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measure- ment conditions listed in the relevant tables. de- signers should check that the operating conditions in their projects match the measurement condi- tions when using the quoted parameters. table 3. operating and ac measurement conditions note: output hi-z is defined as the point where data is no longer driven. figure 5. ac measurement i/o waveform table 4. capacitance note: 1. effective capacitance measured with power supply at 5v; sampled only, not 100% tested. 2. at 25c, f = 1mhz. 3. outputs deselected. parameter M41T80 supply voltage (v cc ) 2.0 to 5.5v ambient operating temperature (t a ) C40 to 85c load capacitance (c l ) 100pf input rise and fall times 50ns input pulse voltages 0.2v cc to 0.8 v cc input and output timing ref. voltages 0.3v cc to 0.7 v cc ai02568 0.8v cc 0.2v cc 0.7v cc 0.3v cc symbol parameter (1,2) min max unit c in input capacitance 7 pf c out (3) output capacitance 10 pf t lp low-pass filter input time constant (sda and scl) 50 ns
M41T80 6/20 table 5. dc characteristics note: 1. valid for ambient operating temperature: t a = C40 to 85c; v cc = 2.0 to 5.5v (except where noted). 2. at 25c. 3. for irq /ft/out, rst , and 32khz pins (open drain) table 6. crystal electrical characteristics note: 1. externally supplied if using the so8 package. stmicroelectronics recommends the kds dt-38: 1ta/1tc252e127, tuning fork type (thru-hole) or the dmx-26s: 1tjs125fh2a212, (smd) quartz crystal for industrial temperature operations. kds can be con- tacted at kouhou@kdsj.co.jp or http://www.kdsj.co.jp for further information on this crystal type. 2. load capacitors are integrated within the M41T80. circuit board layout considerations for the 32.768 khz crystal of minimum t race lengths and isolation from rf generating signals should be taken into account. symbol parameter test condition (1) min typ max unit i li input leakage current 0v v in v cc 1 a i lo output leakage current 0v v out v cc 1 a i cc1 supply current switch freq (scl) = 400khz 3.0v 30 a 5.5v 200 a i cc2 (2) supply current (standby) all inputs = v cc C 0.2v switch freq (scl) = 0hz 32ke = 1 or sqwe = 1 3.0v 1.8 3.0 a 5.5v 35 a 32ke = 0 and sqwe = 0 3.0v 1.5 2.4 a 5.5v 31 a v il input low voltage C0.3 0.3v cc v v ih input high voltage 0.7v cc v cc + 0.3 v v ol output low voltage i ol = 3.0ma 0.4 v output low voltage (open drain) (3) i ol = 10ma 0.4 v sym parameter (1,2) min typ max units f o resonant frequency 32.768 khz r s series resistance 60 k c l load capacitance 12.5 pf
7/20 M41T80 operation the M41T80 clock operates as a slave device on the serial bus. access is obtained by implementing a start condition followed by the correct slave ad- dress (d0h). the 20 bytes contained in the device can then be accessed sequentially in the following order: 1. tenths/hundredths of a second register 2. seconds register 3. minutes register 4. century/hours register 5. day register 6. date register 7. month register 8. year register 9. control register 10. 32ke bit 11 - 16. alarm registers 17 - 19. reserved 20 - square wave register 2-wire bus characteristics the bus is intended for communication between different ics. it consists of two lines: a bi-direction- al data signal (sda) and a clock signal (scl). both the sda and scl lines must be connected to a positive supply voltage via a pull-up resistor. the following protocol has been defined: C data transfer may be initiated only when the bus is not busy. C during data transfer, the data line must remain stable whenever the clock line is high. C changes in the data line, while the clock line is high, will be interpreted as control signals. accordingly, the following bus conditions have been defined: bus not busy. both data and clock lines remain high. start data transfer. a change in the state of the data line, from high to low, while the clock is high, defines the start condition. stop data transfer. a change in the state of the data line, from low to high, while the clock is high, defines the stop condition. data valid. the state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line may be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number of data bytes transferred between the start and stop conditions is not limited. the information is transmitted byte-wide and each receiver acknowl- edges with a ninth bit. by definition a device that gives out a message is called transmitter, the receiving device that gets the message is called receiver. the device that controls the message is called master. the de- vices that are controlled by the master are called slaves. acknowledge. each byte of eight bits is followed by one acknowledge bit. this acknowledge bit is a low level put on the bus by the receiver whereas the master generates an extra acknowledge relat- ed clock pulse. a slave receiver which is ad- dressed is obliged to generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is a stable low dur- ing the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. a master receiver must sig- nal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this case the transmitter must leave the data line high to enable the master to generate the stop condition.
M41T80 8/20 figure 6. serial bus data transfer sequence figure 7. acknowledgement sequence ai00587 data clock data line stable data valid start condition change of data allowed stop condition ai00601 data output by receiver data output by transmitter scl from master start clock pulse for acknowledgement 12 89 msb lsb
9/20 M41T80 figure 8. bus timing requirements sequence table 7. ac characteristics note: 1. valid for ambient operating temperature: t a = C40 to 85c; v cc = 2.0 to 5.5v (except where noted). 2. transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of scl. sym parameter (1) min typ max units f scl scl clock frequency 0 400 khz t low clock low period 1.3 s t high clock high period 600 ns t r sda and scl rise time 300 ns t f sda and scl fall time 300 ns t hd:sta start condition hold time (after this period the first clock pulse is generated) 600 ns t su:sta start condition setup time (only relevant for a repeated start condition) 600 ns t su:dat (2) data setup time 100 ns t hd:dat data hold time 0 s t su:sto stop condition setup time 600 ns t buf time the bus must be free before a new transmission can start 1.3 s ai00589 sda p tsu:sto tsu:sta thd:sta sr scl tsu:dat tf thd:dat tr thigh tlow thd:sta tbuf s p
M41T80 10/20 read mode in this mode the master reads the M41T80 slave after setting the slave address (see figure 10, page 10). following the write mode control bit (r/w =0) and the acknowledge bit, the word ad- dress 'an' is written to the on-chip address pointer. next the start condition and slave address are repeated followed by the read mode control bit (r/w =1). at this point the master transmitter be- comes the master receiver. the data byte which was addressed will be transmitted and the master receiver will send an acknowledge bit to the slave transmitter. the address pointer is only increment- ed on reception of an acknowledge clock. the M41T80 slave transmitter will now place the data byte at address an+1 on the bus, the master re- ceiver reads and acknowledges the new byte and the address pointer is incremented to an+2. this cycle of reading consecutive addresses will continue until the master receiver sends a stop condition to the slave transmitter. the system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). the update will resume due to a stop condition or when the pointer increments to any non-clock address (08h-13h). note: this is true both in read mode and write mode. an alternate read mode may also be implement- ed whereby the master reads the M41T80 slave without first writing to the (volatile) address point- er. the first address that is read is the last one stored in the pointer (see figure 11, page 11). figure 9. slave address location figure 10. read mode sequence ai00602 r/w slave address start a 01000 11 msb lsb ai00899 bus activity: ack s ack ack ack no ack stop start p sda line bus activity: master r/w data n data n+1 data n+x word address (an) slave address s start r/w slave address ack
11/20 M41T80 figure 11. alternative read mode sequence write mode in this mode the master transmitter transmits to the M41T80 slave receiver. bus protocol is shown in figure 12, page 11. following the start con- dition and slave address, a logic '0' (r/w =0) is placed on the bus and indicates to the addressed device that word address an will follow and is to be written to the on-chip address pointer. the data word to be written to the memory is strobed in next and the internal address pointer is incremented to the next address location on the reception of an acknowledge clock. the M41T80 slave receiver will send an acknowledge clock to the master transmitter after it has received the slave address see figure 9, page 10 and again after it has re- ceived the word address and each data byte. figure 12. write mode sequence ai00895 bus activity: ack s ack ack ack no ack stop start p sda line bus activity: master r/w data n data n+1 data n+x slave address ai00591 bus activity: ack s ack ack ack ack stop start p sda line bus activity: master r/w data n data n+1 data n+x word address (an) slave address
M41T80 12/20 clock operation the M41T80 is driven by a quartz-controlled oscil- lator with a nominal frequency of 32,768hz. the accuracy of the real time clock depends on the frequency of the quartz crystal that is used as the time-base for the rtc. the 20-byte register map (see table 8, page 13) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. tenths/hundredths of seconds, seconds, minutes, and hours are contained within the first four registers. note: a write to any clock register will result in the tenths/hundredths of seconds being reset to 00, and tenths/hundredths of seconds cannot be written to any value other than 00. bits d6 and d7 of clock register 03h (century/ hours register) contain the century enable bit (ceb) and the century bit (cb). setting ceb to a '1' will cause cb to toggle, either from '0' to '1' or from '1' to '0' at the turn of the century (de- pending upon its initial state). if ceb is set to a '0,' cb will not toggle. bits d0 through d2 of register 04h contain the day (day of week). registers 05h, 06h, and 07h contain the date (day of month), month and years. the ninth clock register is the control register. bit d7 of register 01h contains the stop bit (st). setting this bit to a '1' will cause the oscillator to stop. if the device is expected to spend a significant amount of time on the shelf, the oscillator may be stopped to reduce current drain. when reset to a '0' the oscillator restarts within four seconds (typically one second). the eight clock registers may be read one byte at a time, or in a sequential block. provision has been made to assure that a clock update does not occur while any of the eight clock addresses are being read. if a clock address is being read, an update of the clock registers will be halted. this will prevent a transition of data during the read. timekeeper ? registers the M41T80 offers 20 internal registers which contain clock, alarm, 32khz, flag, square wave, and control data. these registers are memory lo- cations which contain external (user accessible) and internal copies of the data (usually referred to as biport ? timekeeper cells). the external copies are independent of internal functions ex- cept that they are updated periodically by the si- multaneous transfer of the incremented internal copy. the internal divider (or clock) chain will be reset upon the completion of a write to any clock address. the system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). the update will resume ei- ther due to a stop condition or when the pointer increments to any non-clock address (08h-13h). timekeeper and alarm registers store data in bcd. control, 32khz, and square wave registers store data in binary format.
13/20 M41T80 table 8. timekeeper ? register map keys: st = stop bit 0 = must be set to '0' 32ke = 32khz enable bit ceb = century enable bit cb = century bit out = output level afe = alarm flag enable flag rpt1-rpt5 = alarm repeat mode bits af = alarm flag (read only) sqwe = square wave enable rs0-rs3 = sqw frequency addr function/range bcd format d7 d6 d5 d4 d3 d2 d1 d0 00h 0.1 seconds 0.01 seconds 10s/100s of seconds 00-99 01h st 10 seconds seconds seconds 00-59 02h 0 10 minutes minutes minutes 00-59 03h ceb cb 10 hours hours (24 hour format) century/ hours 0-1/00-23 04h 0 0 0 0 0 day of week day 01-7 05h 0 0 10 date date: day of month date 01-31 06h 0 0 0 10m month month 01-12 07h 10 years year year 00-99 08h out 0 0 0 0000 control 09h 32ke 0 0 0 0 0 0 0 32khz 0ah afe sqwe 0 al 10m alarm month al month 01-12 0bh rpt4 rpt5 ai 10 date alarm date al date 01-31 0ch rpt3 0 ai 10 hour alarm hour al hour 00-23 0dh rpt2 alarm 10 minutes alarm minutes al min 00-59 0eh rpt1 alarm 10 seconds alarm seconds al sec 00-59 0fh 0 af 0 0 0 0 0 0 flags 10h 0 0 0 0 0 0 0 0 reserved 11h 0 0 0 0 0 0 0 0 reserved 12h 0 0 0 0 0 0 0 0 reserved 13h rs3 rs2 rs1 rs0 0 0 0 0 sqw
M41T80 14/20 setting alarm clock registers address locations 0ah-0eh contain the alarm set- tings. the alarm can be configured to go off at a prescribed time on a specific month, date, hour, minute, or second or repeat every year, month, day, hour, minute, or second. bits rpt5-rpt1 put the alarm in the repeat mode of operation. table 9, page 14 shows the possible configurations. codes not listed in the table default to the once per second mode to quickly alert the user of an incorrect alarm setting. when the clock information matches the alarm clock settings based on the match criteria defined by rpt5-rpt1, the af (alarm flag) is set. if afe (alarm flag enable) is also set (and sqwe is '0.'), the alarm condition activates the irq /out/sqw pin. note: if the address pointer is allowed to incre- ment to the flag register address, an alarm con- dition will not cause the interrupt/flag to occur until the address pointer is moved to a different ad- dress. it should also be noted that if the last ad- dress written is the alarm seconds, the address pointer will increment to the flag address, causing this situation to occur. the irq /out/sqw output is cleared by a read to the flags register as shown in figure 13. a subsequent read of the flags register is neces- sary to see that the value of the alarm flag has been reset to '0.' figure 13. alarm interrupt reset waveform table 9. alarm repeat modes rpt5 rpt4 rpt3 rpt2 rpt1 alarm setting 1 1 1 1 1 once per second 1 1 1 1 0 once per minute 1 1 1 0 0 once per hour 1 1 0 0 0 once per day 1 0 0 0 0 once per month 0 0 0 0 0 once per year irq/out/sqw active flag 0fh 0eh 10h high-z ai07021
15/20 M41T80 table 10. square wave output frequency full-time 32khz square wave output the M41T80 offers the user a special 32khz square wave function which defaults to output on the f 32k pin (pin 3) as long as v cc is valid, and the oscillator is running (st bit = '0'). this function is available within four seconds of initial power-up and can only be disabled by setting the 32ke bit to '0' or the st bit to '1.' if not used, the f 32k pin should be disconnected and allowed to float. note: the f 32k pin is an open drain which requires an external pull-up resistor. square wave bits square wave rs3 rs2 rs1 rs0 frequency units 0000none- 0 0 0 1 32.768 khz 0 0 1 0 8.192 khz 0 0 1 1 4.096 khz 0 1 0 0 2.048 khz 0 1 0 1 1.024 khz 0110512hz 0111256hz 1000128hz 100164hz 101032hz 101116hz 11008hz 11014hz 11102hz 11111hz
M41T80 16/20 century bit bits d7 and d6 of clock register 03h contain the century enable bit (ceb) and the century bit (cb). setting ceb to a '1' will cause cb to tog- gle, either from a '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). if ceb is set to a '0,' cb will not toggle. output driver pin when the afe bit and sqwe bit are not set, the irq /out/sqw pin becomes an output driver that reflects the contents of d7 of the control register. in other words, when d7 (out bit) of address lo- cation 08h is a '0,' then the irq /out/sqw pin will be driven low. note: the irq /out/sqw pin is an open drain which requires an external pull-up resistor. preferred power-on default when powering the device up from ground (0v), the following register bits are set to a '0' state: st; afe; and sqwe. the following bits are set to a '1' state: out and 32ke (see table 11, page 16). table 11. preferred power-on default values note: 1. if v cc falls to a voltage, 0v < v cc < 2.0v, these bits should be rewritten by the user. condition st out afe sqwe 32ke power-up (1) 01001
17/20 M41T80 part numbering table 12. ordering information scheme for a list of available options (e.g., speed, package) or for further information on any aspect of this device, please contact the st sales office nearest to you. example: m41t 80 m 6 tr device type m41t supply voltage and write protect voltage 80 = v cc = 2.0 to 5.5v package m = so8 temperature range 6 = C40c to 85c shipping method for soic blank = tubes tr = tape & reel
M41T80 18/20 package mechanical information figure 14. so8 C 8 lead plastic small outline, 150 mils body width, package mechanical drawing note: drawing is not to scale. table 13. so8 C 8-lead plastic small outline, 150 mils body width, package mechanical data symb mm inches typ min max typ min max a C 1.35 1.75 C 0.053 0.069 a1 C 0.10 0.25 C 0.004 0.010 b C 0.33 0.51 C 0.013 0.020 c C 0.19 0.25 C 0.007 0.010 d C 4.80 5.00 C 0.189 0.197 ddd C C 0.10 C C 0.004 e C 3.80 4.00 C 0.150 0.157 e 1.27 C C 0.050 C C h C 5.80 6.20 C 0.228 0.244 h C 0.25 0.50 C 0.010 0.020 l C 0.40 0.90 C 0.016 0.035 C08C08 n8 8 so-a e 8 ddd b e a d c l a1 1 h h x 45? a2
19/20 M41T80 revision history table 14. document revision history date rev. # revision details october 2002 1.0 first issue
M41T80 20/20 M41T80, 41t80, t80, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, ser ial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, ac- cess, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, a ccess, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, ac- cess, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, a ccess, interface, interface, inter- face, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interf ace, interface, interface, interface, interface, inter- face, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interf ace, interface, interface, interface, interface, inter- face, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, cl ock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, c lock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, c lock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, c lock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, c lock, clock, clock, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rt c, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rt c, rtc, rtc, rtc, rtc, rtc, rtc, rtc, programmable, programmable, programmable, programmable, programmable, programmable, programmable, prog rammable, program- mable, programmable, programmable, programmable, programmable, programmable, programmable, programmable, programmable, programm able, programmable, programmable, programmable, programmable, programmable, programmable, programmable, programmable, programmable, programmable, p rogrammable, pro- grammable, programmable, programmable, programmable, programmable, programmable, programmable, programmable, programmable, prog rammable, program- mable, programmable, programmable, programmable, programmable, programmable, programmable, programmable, programmable, programm able, programmable, programmable, programmable, programmable, programmable, programmable, programmable alarm, programmable alarm, programmable alar m, programmable alarm, programmable alarm, programmable alarm, programmable alarm, programmable alarm, programmable alarm, programmable alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, a larm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, a larm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, a larm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, a larm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, inte rrupt, interrupt, interrupt, interrupt, interrupt, inter- rupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interr upt, interrupt, interrupt, interrupt, interrupt, interrupt, in- terrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrup t, interrupt, interrupt, interrupt, interrupt, interrupt, inter- rupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interr upt, interrupt, interrupt, interrupt, interrupt, interrupt, in- terrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrup t, interrupt, interrupt, interrupt, interrupt, interrupt, inter- rupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interr upt, interrupt, interrupt, interrupt, interrupt, interrupt, in- terrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrup t, interrupt, interrupt, interrupt, interrupt, interrupt, inter- rupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, watchdog, w atchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdo g, watchdog, watch- dog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, wa tchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdo g, watchdog, watch- dog, watchdog, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , switchover, switchover, switchover, switchover, switchover, switchover, switchover, switchover, switchover, backup, backup, backup, backup, backup, backup, backup, backup, backup, backup, backup, bac kup, backup, backup, backup, backup, backup, backup, backup, backup, write protect, write protect, write protect, write protect, write protect, write protec t, write protect, write protect, write protect, write protect, write protect, write protect, write protect, write protect, write protect, write protect, write protect , write protect, write protect, write protect, write protect, write protect, write protect, write protect, write protect, industrial, industrial, industrial, industrial, indu strial, industrial, industrial, industrial, industrial, industrial, industrial, vindustrial, industrial, industrial, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, sna phat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, soic, soic, soic, s o- ic, soic, soic, soic, soic, soic, soic, soic, soic, soic, soic, soic information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners. ? 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. www.st.com

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